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> 1.3 gbps ethernet transceiver TLK1211 fast relock
1.3 gbps ethernet transceiver TLK1211 fast relock
* 0.6-Gbps to 1.3-Gbps Serializer/Deserializer
* Low Power Consumption <250 mW (typ) at 1.25 Gbps
* Fast Relock Times Less Than 256 ns (Typ) Suitable for EPON/GEPON Applications
* LVPECL CompatibleDifferential I/O on High Speed Interface
* Single Monolithic PLL Design
* Support For 10-Bit Interface or Reduced Interface 5-Bit DDR (Double Data Rate) Clocking
* Receiver Differential Input Thresholds 200 mV Minimum
* IEEE 802.3 Gigabit Ethernet Compliant
* ANSI X3.230-1994 (FC-PH) Fibre Channel Compliant
* Advanced 0.25- m CMOS Technology
* No External Filter Capacitors Required
* Comprehensive Suite of Built-In Testability
* IEEE 1149.1 JTAG Support
* 2.5-V Supply Voltage for Lowest Power Operation
* 3.3-V Tolerant on LVTTL Inputs
* 64-Pin VQFP With Thermally Enhanced Package (PowerPAD )
* CPRI Data Rate Compatible (614 Mbps, 1.22 Gbps)
* Industrial Temperature Range Supported: -40 C to 85 C
The TLK1211RCP gigabit ethernet transceiver provides for ultrahigh-speed, full-duplex, point-to-point data transmissions. This device is based on the timing requirements of the 10-bit interface specification by the IEEE 802.3 gigabit ethernet specification and is also compliant with the ANSI X3.230-1994 (FC-PH) fibre channel standard. The device supports data rates from 0.6 Gbps to 1.3 Gbps.
The primary application of the transceiver is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50 ohm. The transmission media can be printed-circuit board traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
The transceiver performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface.
The transceiver supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte.
In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned on both the rising and falling edges of the reference clock. The data is clocked most significant bit first (bits 0-4 of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits 5-9 of the 8b/10b encoded data) are clocked on the falling edge of the clock.
The transceiver provides a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported.
